The present invention relates to the manufacture of micro-structures and, more specifically, to the manufacture of micro-structures using a method that provides accurate patterning and reduced overlay error, as well as accurate lithography over extreme topography.
The manufacture of micro-structures, such as micro-electromechanical structures (MEMS) or optical devices, such as transmitters/receivers, require precise placement of components. In the case of an optical device, for example, these components typically include a laser diode, a monitor photodiode, lenses, mirrors, isolators and optical fibers. Accurate positioning of the components can be achieved by the use of another micro-structure, called an optical bench. An optical bench consists of etched cavities, sockets, grooves, etc. into which the optical components are placed. The cavities accommodate the components and provide accurate positioning of the parts in all three axes.
Conventionally, cavity areas to be etched are first patterned individually by lithography. Lithography includes the use of photographic techniques to register particular cavity areas on a substrate, such as silicon. Generally, light is emitted through a mask to outline a pattern of a cavity area onto a film residing on a substrate, such as a silicon substrate. In this manner, the pattern of the cavity areas to be etched is transferred onto the film to create a hard mask on the substrate.
Different physical characteristics of the cavities to be etched typically require different fabrication techniques. This usually means that each of the cavities are processed separately, using successive lithography steps.
For example, cavity areas that are required to have vertical side walls are typically etched by reactive ion etching (RIE), while cavities with sloped side walls may be achieved by anisotropic wet etching. In addition, all of the cavities are usually not of the same depth, and thus cannot be etched in a single etch step. Also, the opening of the cavity (x,y dimension) affects the etch rate and thus the depth of the cavity (z dimension). This effect is particularly noticeable for dry etching. Since not all cavities have the same opening but may require the same depth, their etching is carried out in separate steps.
The use of multiple lithographic steps can create difficulties. For example, each lithography step can introduce an overlay error due to misalignment of the mask with respect to previous masks. A misaligned cavity would cause an optical component to be positioned off the optical axis. The main cause for misalignment is the overlay error associated with multiple lithographic steps.
Also, after the etching of the first set of cavities, the bench surface is no longer planar and would typically exhibit extreme topography. The extreme topography causes difficulty in obtaining uniform photoresist coverage in subsequent mask exposures. Moreover, the depth of focus will vary due to the topography, and thus the obtained resolution will degrade.
Accordingly, a need exists for an improved method of manufacture of micro-structures that avoids the pitfalls of conventional methods, including overlay error and the need for accurate lithography over extreme topography.
The present invention provides methods for manufacture of micro-structures, such as MEMS or silicon optical benches. In one aspect of the invention, the method includes using a single mask to pattern two or more cavity areas to be etched into a substrate in different etching steps, and then selectively choosing the cavity areas for etching.
In a preferred embodiment, the method includes patterning a substrate to identify a plurality of cavity areas to be etched into the substrate and filling at least one-of the cavity areas with a distinctive filler material. Filler material is chemically distinctive in the sense that it can be etched selectively with respect to the other filling materials. At least one of the cavity areas containing a distinctive filler material is then chosen based at least in part on the distinctive filler material. The chosen cavity area is then etched.
In a preferred embodiment, filling a cavity area with a distinctive filler material includes: (a) filling a plurality of cavity areas with a first filler material; (b) protecting at least the cavity areas containing first filler material with a protective material, leaving first filler material of at least one cavity area unprotected; (c) removing said unprotected first filler material to form an exposed cavity area; (d) removing the protective material; and (e) adding a distinctive filler material to said exposed cavity area.
In another preferred embodiment, two different distinctive filler materials are applied to the cavity areas in an alternating sequence. It is preferred that the cavities be filled with the filler materials in a sequence that is opposite the sequence in which the cavities are to be etched. In this way, the cavity areas can be selectively etched without affecting other cavity areas to be etched separately. It is preferred that the method further include: (a) filling with a first filler material said plurality of cavity areas to be etched in an etching sequence; (b) protecting with a protecting material at least one unprotected cavity area and any previously protected cavity areas, said protecting performed in a sequence opposite the etching sequence; (c) removing the first filler material from remaining unprotected cavity areas; (d) removing said protecting material deposited in step (b); (e) filling with a second filler material said plurality of cavity areas to be etched in an etching sequence; (f) protecting with a protecting material at least one unprotected cavity area and any previously protected cavity areas, said protecting performed in a sequence opposite the etching sequence; (g) removing the second filler material from remaining unprotected cavity areas; (h) removing said protecting material deposited in step (f); and (i) repeating steps (a) through (h) for all but the first cavity area to be etched in the etching sequence, such that the substrate within said first cavity area to be etched is exposed by removing said first filler material in step (c) or removing said second filler material in step (g).
The methods of the invention minimize overlay error and circumvent the need for accurate lithography over extreme topography. The methods provided herein also allow for accurate dimensional control in the presence of such extreme topography. Precision lithography is not required after the initial mask, which provides exact registry of all the cavities with respect to each other. All lithographic steps are carried out on flat surfaces. Additionally, the method of the invention permits the incorporation of metal traces and metal patterns on top of a surface having non-planar portions.
In another aspect of the invention, novel micro-structures are provided. As mentioned above, the micro-structures provided by the process of the invention have more accurately defined cavity areas as compared to micro-structures manufactured by conventional means. The increased accuracy is achieved, at least in part, by avoiding overlay error and the need for accurate lithography over extreme topography. The micro-structures are formed in accordance with a process as outlined above, and described further herein.
The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of preferred embodiments of the invention, with reference to the drawings.
FIG. 1 illustrates a conventional silicon bench, having five different types of cavities etched into it.
FIG. 2(a)-(c) illustrates patterning of a substrate, deposition of a first filler layer, and planarization of the first filler layer as part of a method in accordance with the present invention.
FIG. 3(a)-(d) illustrates depositing distinctive filler layers in accordance with the present invention.
FIG. 4(a)-(c) illustrates depositing filler material using a lift-off process in accordance with the present invention.
FIG. 5(a)-(c) illustrates selective simultaneous etching of cavities c3 and c4 and passivation of the etched cavities in accordance with the present invention.
FIG. 6(a)-(c) illustrates the selective etching of cavity c1 in accordance with the present invention.
FIG. 7(a)-(c) illustrates the selective etching of cavities c2 and c5 in accordance with the present invention.
FIG. 8(a)-(c) illustrates a method of the invention utilizing a lift-off process for depositing filler material, but without planarization.
FIG. 9(a)-(c) illustrates a method of the invention using masking and etching to deposit the filler materials, but without planarization.
FIG. 10 illustrates filler material deposited in areas c1, c2, and c5 without planarization.
FIG. 11(a)-(c) illustrates the deposition of a hard mask, deposition of a first filler material, and deposition of a photoresist over cavity area c5 in accordance with the present invention.
FIG. 12(a)-(c) illustrates the removal of the first filler material, removal of the photoresist, addition of a second filler material, and addition of a photoresist over cavity areas c5 and c2.
FIG. 13(a)-(c) illustrates the removal of the second filler material, removal of the photoresist, addition of the first filler material, and addition of a photoresist over cavity areas c5, c2, and c1.
FIG. 14(a)-(b) illustrates the etching of cavity areas c3 and c4, and passivation of the etched cavities in accordance with the present invention.
FIG. 15(a)-(b) illustrates the removal of first filler material, and etching and passivation of cavity c1 in accordance with the present invention.
FIG. 16(a)-(b) illustrates the removal of second filler material, and etching and passivation of cavity c2 in accordance with the present invention.
FIG. 17(a)-(b) illustrates the removal of first filler material, and etching and passivation of cavity c5 in accordance with the present invention.
FIG. 18(a)-(c) illustrates creating a hard mask, depositing filler material that is planarized, depositing photoresist on all but cavities c3 and c4, and etching and passivating cavities c3 and c4 in accordance with the present invention.
FIG. 19(a)-(b) illustrates depositing photoresist on all but cavity c1, and etching and passivating cavity c1 in accordance with the present invention.
FIG. 20(a)-(b) illustrates depositing photoresist on all but cavity c2, and etching and passivating cavity c2 in accordance with the present invention.
FIG. 21(a)-(b) illustrates depositing photoresist on all but cavity c5, and etching and passivating cavity c5 in accordance with the present invention.
FIG. 22(a)-(c) illustrates a silicon wafer coated with a three layer dielectric stack with a coating of photoresist over cavities c1, c2, and c5 in accordance with the present invention.
FIG. 23(a)-(c) illustrates etching and passivating cavities c3 and c4, and adding photoresist over all but cavity area c2 in accordance with the present invention.
FIG. 24(a)-(c) illustrates etching and passivating cavity c2 in accordance with the present invention.
FIG. 25(a)-(c) illustrates depositing a photoresist on all but cavity area c1, etching and passivating cavity c1, and deposition of metal in cavity c1 in accordance with the present invention.
FIG. 26(a)-(c) illustrates removing excess metal from cavity area c1 and depositing a photoresist over all cavity areas but cavity area c5 in accordance with the present invention.
FIG. 27(a)-(c) illustrates etching cavity c5 through the substrate and removing the photoresist.